Content in this edit is translated from the existing Chinese Wikipedia article at [[:zh:制程-架构-优化模型]]; see its history for attribution.
{{Translated|zh|制程-架构-优化模型}}
Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.[1][2][3][4][5]
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