The hyperSPARC was introduced in 1993, and competed with the Sun MicrosystemsSuperSPARC. Raju Vegesna was the microarchitect. The hyperSPARC was Sun Microsystem's primary competitor in the mid-1990s. When Fujitsu acquired Ross from Cypress, the hyperSPARC was considered to be more important by its new owner than the SPARC64 developed by HAL Computer Systems, also a Fujitsu subsidiary, a view which was shared with analysts.
Description
Ross hyperSPARC II CPU die photo
The hyperSPARC was a two-way superscalar microprocessor. It had four execution units: an integer unit, a floating-point unit, a load/store unit and a branch unit. The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded. The decoder could not decode new instructions if the previously decoded instructions were not issued to the execution units.
The integer register file contained 136 registers, providing eight register windows, a feature defined in the SPARC ISA. It had two read ports. The integer unit had a four-stage pipeline, of which two stages were added so the pipeline would be equal to all non-floating-point pipelines. Integer multiply and divide, instructions added in the V8 version of the SPARC architecture, had an 18- and 37-cycle latency, respectively, and stalled the pipeline until they were completed.
The hyperSPARC consists of 1.2 million transistors. It was fabricated by Cypress in their 0.65 μm, two-layer metal, complementary metal–oxide–semiconductor (CMOS) process. Later iterations of the hyperSPARC have more transistors due to new features, and were ported to newer processes. They were fabricated by Fujitsu, except for the last iteration, which was fabricated by NEC.
The hyperSPARC used the Cypress SparcSet chipset which was introduced in late July 1992. It was developed by Santa Clara, California start-up Nimbus Technologies, Inc. for Cypress, who fabricated the design. SparcSet was also compatible with other SPARC microprocessors.
