Talk:Parallel RAM

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QUOTING FROM: Algorithms and Theory of Computation Handbook, CRC Press LLC, 1999, "parallel random-access machine", in Dictionary of Algorithms and Data Structures [online], Paul E. Black, ed., U.S. National Institute of Standards and Technology. 27 February 2004. (accessed 6/4/06) Available from: http://www.nist.gov/dads/HTML/parallelRandomAccessMachine.html:

parallel random-access machine (definition)

Definition: A shared memory model of computation, where typically the processors all execute the same instruction synchronously, and access to any memory location occurs in unit time.

Also known as PRAM.

See also work-depth model, multiprocessor model.

PLEASE OBSERVE: that the definition clearly indicates use of the SIMD machine and ***not*** an MIMD machine as this Wiki entry states. Vonkje 16:10, 3 June 2006 (UTC)Reply

The definition you prodivded is wrong. If that definition was true, PRAMs would be virtualy useless for examination of any serious (i.e. the one which has conditional statement in it) paralel algorithm. And PRAMs are used for examination of those. --Dijxtra 17:59, 27 June 2006 (UTC)Reply

In SIMD, conditional statements are executed using predication. In other words, the fact that an algorithm has a conditional statement does not mean that it cannot be executed on a SIMD machine. -- 69.11.220.126 (talk) 21:52, 7 November 2013 (UTC)Reply

That is a definition of SIMD, indeed. Nevertheless, a wrong definition does not prove the otherwise, namely that PRAM is MIMD. The "Advanced Computer Architecture and Parallel Processing, 2005" also states that "Active processors must execute the same instruction, generally, on different data. Hence, this model is sometimes called the shared memory, single instruction, multiple data (SMSIMD) machine." The Google is full of presentations stating "the abstract PRAM model can be SIMD or MIMD". There is no ground for the MIMD-thesis, therefore. --Javalenok (talk) 17:52, 20 March 2009 (UTC)Reply

NVIDIA's CUDA programming model provides a parallel data cache within a single "cooperative thread array" (CTA, aka thread block). All threads within the CTA have CRCW access to the parallel data cache, so one CTA is effectively a PRAM machine (with an installed base of millions!). However, CTAs are currently limited to 512 threads. Skadron 17:11, 15 November 2007 (UTC)Reply

I don't agree that CUDA is a PRAM implementation. This is because: 1. The PRAM model is a generalization of the Random Access Machine (RAM) model, the basic sequential computing model exposed to programmers in traditional programming languages. 2. The NVIDIA CUDA model cannot support the PRAM since it does not support the RAM.