Talk:Explicit data graph execution
Current version [1] sounds a bit too much marketing: enthusiastic, all positive, too abstract, long lead-in. Musaran (talk) 16:16, 21 November 2023 (UTC)Reply
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Marketing-ish
Current version [1] sounds a bit too much marketing: enthusiastic, all positive, too abstract, long lead-in. Musaran (talk) 16:16, 21 November 2023 (UTC)
Registers & ALUs details please
These look dubious and/or requires more explanation:
each basic block is given its own local registers
This is bound to make them either too scarce or wasteful, a know problem of independent unit design.
And does not address how data is passed between blocks/engines.
an EDGE CPU would normally consist of a single type of ALU-like unit.
Floating-point or division are known to be complex and have a big footprint, while a lot of code does not use them. One would expect hyperblocks dispatched to specialized engines ; or identical engines to dispatch operations to shared parallel execution units ; or maybe a slow but highly parallel microcode implementation. Musaran (talk) 16:44, 21 November 2023 (UTC)
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