Talk:Double data rate

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This page desperately needs a rewrite - I've corrected content, but don't have the time available currently to produce material up to the wikipedia standard. --Odii 11:14, August 1, 2005 (UTC)

I disagree with this bit:

therefore there is justification for saying that e.g. 200 MHz DDR memory has a "400 MHz bus speed" -- it actually does have, for the data lines.

The author seems to have missed the point of why it's inaccurate to use Hertz to refer to the data rate. It's not because only the data lines are operating at this speed; it's because Hertz is cycles per second and the data lines don't cycle, they transfer arbitrary data. Therefore MT/s or sometimes Mbit/s should be used. In fact this line pretty much contradicts what's written earlier in the article about careful usage of units. --80.189.138.93 (talk) 11:16, 25 February 2010 (UTC)Reply

effectively doubling the data transmission rate without having to deal with the additional problems of timing skew that increasing the number of data lines would introduce

Isn't the more-direct alternative increasing the actual clock rate? What's the reason for doubling the data rate but using the same clock? --Dtcdthingy 11:22, 28 Apr 2005 (UTC)

It's probably done to keep component cost down, and allow for line encoding that isn't synchronous, such as NRZI. A higher clock rate would make encoding like NRZI practically impossible without some sort of self-synchronising overlaying encoding scheme, and components to maintain it would be more costly and less reliable. 83.95.6.246 11:14, 5 November 2007 (UTC)Reply

Bus Size's Effect on DDR-xxx PC-xxxx Designation

The article gave an example that DDR memory clocked at 100MHz would transfer data at 200MHz (DDR-200) and would be designated PC-1600. How is the 1600 derived from the 100MHz? Is this assuming a 16-bit word size?

See DDR SDRAM. Conf 13:14, 26 October 2005 (UTC)Reply

So the data is sent on both rising and falling edges. How about the addresses? Are they accepted at the same double (two-edge) rate, or is only one address accepted and two bits (or words) of data accessed from, say, successive memory locations for each address accepted? -R. S. Shaw 06:42, 29 October 2005 (UTC)Reply

This article discusses double data rate exclusively. As far as I understand, the design of DDR SDRAM memory technology relies on caching. Requested data is returned in a series (burst) of something like 4 or 8 transfers, some time after the request. The difference between SDR and DDR is that this burst is sent twice as fast, one transfer per clock tick, instead of one transfer per two clock ticks (SDR). Issuing requests is much slower anyway. I am basically restating this. Conf 16:24, 31 October 2005 (UTC)Reply

I suggest we move the contents of this article and the one on QDR into Pumping (computer systems). This will tidy up by reducing duplication (e.g. how SDR, DDR and QDR relate to each other) and allow us to easily add newer DR techniques such as ODR. If there are good reasons to keep pumping, DDR and QDR as separate articles please put them forward. Guffydrawers (talk) 12:19, 9 November 2015 (UTC)Reply

The Multi-channel memory architecture article says "Dual-channel memory employs two channels. [...] Dual-channel-enabled memory controllers in a PC system architecture use two 64-bit data channels. [...] The memory modules are installed into matching banks, each of which belongs to a different channel.". However, the current Double data rate article says that "DDR should not be confused with dual channel, in which each memory channel accesses two RAM modules simultaneously.", which seems wrong to me as I understand that each memory channel accesses one RAM module but the memory controller unit (MCU) accesses the two (or more) RAM modules simultaneously using channels in parallel.

So I would rewrite this as "DDR should not be confused with dual channel, in which the memory controller unit (MCU) accesses two RAM modules simultaneously using two channels in parallel." (or something like this, sorry I'm not a native English speaker).

Any objection?

EDIT: after more reading, I saw that there was a "ganged" and an "unganged" architecture, where "ganged" apparently refers to interleaved memory, which has been abandoned by the RAM manufacturers apparently as it was not very efficient. So all this topic would probably require way more clarification than I first expected. EDIT 2: not interleaved memory but 2 buses aggregated in one being the sum of the two. We really need more explanations about all this.

— Preceding unsigned comment added by Cluxter (talk • contribs) 20:46, 2 August 2025 (UTC)Reply