Subthreshold conduction

Subthreshold leakage in an nFET

Subthreshold conduction or subthreshold leakage or subthreshold drain current is the current between the source and drain of a MOSFET when the transistor is in subthreshold region, or weak-inversion region, that is, for gate-to-source voltages below the threshold voltage.^[1]

The amount of subthreshold conduction in a transistor is set by its threshold voltage, which is the minimum gate voltage required to switch the device between on and off states. However, as the drain current in a MOS device varies exponentially with gate voltage, the conduction does not immediately become zero when the threshold voltage is reached. Rather it continues showing an exponential behavior with respect to the subthreshold gate voltage. When plotted against the applied gate voltage, this subthreshold drain current exhibits a log-linear slope, which is defined as the subthreshold slope. Subthreshold slope is used as a figure of merit for the switching efficiency of a transistor.^[2]

In digital circuits, subthreshold conduction is generally viewed as a parasitic leakage in a state that would ideally have no conduction. In micropower analog circuits, on the other hand, weak inversion is an efficient operating region, and subthreshold is a useful transistor mode around which circuit functions are designed.^[3]

Historically, in CMOS circuits, the threshold voltage has been insignificant compared to the full range of gate voltage between the ground and supply voltages, which allowed for gate voltages significantly below the threshold in the off state. As gate voltages scaled down with transistor size, the room for gate voltage swing below the threshold voltage drastically reduced, and the subthreshold conduction became a significant part of the off-state leakage of a transistor.^[4][5] For a technology generation with threshold voltage of 0.2 V, subthreshold conduction, along with other leakage modes, can account for 50% of total power consumption.^[6][7]

Sub-threshold electronics

Some devices exploit sub-threshold conduction to process data without fully turning on or off. Even in standard transistors a small amount of current leaks even when they are technically switched off. Some sub-threshold devices have been able to operate with between 1 and 0.1 percent of the power of standard chips.^[8]

Such lower power operations allow some devices to function with the small amounts of power that can be scavenged without an attached power supply, such as a wearable EKG monitor that can run entirely on body heat.^[8]

See also

• Integrated circuit
• Moore's law
• Multi-channel length
• Subthreshold slope

References

1. Tsividis, Yannis (1999). Operation and Modeling of the MOS Transistor (2 ed.). New York: McGraw-Hill. p. 99. ISBN 0-07-065523-5.
2. Physics of Semiconductor Devices, S. M. Sze. New York: Wiley, 3rd ed., with Kwok K. Ng, 2007, chapter 6.2.4, p. 315, ISBN 978-0-471-14323-9.
3. Vittoz, Eric A. (1996). "The Fundamentals of Analog Micropower Design". In Toumazou, Chris; Battersby, Nicholas C.; Porta, Sonia (eds.). Circuits and systems tutorials. John Wiley and Sons. pp. 365–372. ISBN 978-0-7803-1170-1.
4. Soudris, Dimitrios; Piguet, Christian; Goutis, Costas, eds. (2002). Designing CMOS Circuits for Low Power. Springer. ISBN 1-4020-7234-1.
5. Reynders, Nele; Dehaene, Wim (2015). Written at Heverlee, Belgium. Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits And Signal Processing (ACSP) (1 ed.). Cham, Switzerland: Springer International Publishing AG Switzerland. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.
6. Roy, Kaushik; Yeo, Kiat Seng (2004). Low Voltage, Low Power VLSI Subsystems. McGraw-Hill Professional. Fig. 2.1, p. 44. ISBN 0-07-143786-X.
7. l-Hashimi, Bashir M. A, ed. (2006). System on a Chip: Next Generation Electronics. Institution of Engineering and Technology. p. 429. ISBN 0-86341-552-0.
8. Jacobs, Suzanne (2014-07-30). "A Batteryless Sensor Chip for the Internet of Things". Retrieved 2018-05-01.

Further reading

• Gaudet, Vincent C. (2014-04-01) [2013-09-25]. "Chapter 4.1. Low-Power Design Techniques for State-of-the-Art CMOS Technologies". Written at Freiberg, Germany. In Steinbach, Bernd [in German] (ed.). Recent Progress in the Boolean Domain (1 ed.). Newcastle upon Tyne, UK: Cambridge Scholars Publishing. pp. 187–212. ISBN 978-1-4438-5638-6. Retrieved 2019-08-04. [1] (xxx+428 pages)