Although they use similar peripherals and are marketed as part of the same product line,[1][2] the two architectures are actually quite different.
Both have an 8-bit accumulator used for most operations, plus two 8-bit index registers (X and Y) used for memory addressing. Also both have 8-bit instructions followed by up to 2 bytes of operands, and both have support for manipulating and branching on individual bits of memory.
There, the similarities end.
The ST6 is a Harvard architecture with an 8-bit (256 byte) data address space and a separate 12-bit (4096 byte) program space. Operands are always 1 byte long, and some instructions support two operands, such as "move 8-bit immediate to 8-bit memory address". Subroutine calls are done using a separate hardware stack. Data registers (but not the program counter or flags) are memory-mapped.
The ST6's addressing modes are limited to immediate, 8-bit absolute memory address, and register indirect modes (X) and (Y).
The ST7 is a von Neumann architecture with a single 16-bit (64 kiB) address space. The first 256 bytes of RAM (the zero page) have extra flexibility. There are no two-operand instructions except for "test bit and branch". Its registers are not memory-mapped, and it uses general-purpose RAM (plus a stack pointer register) for subroutine calls.
The ST7 supports a wide variety of addressing modes, including base+index and double-indirect.
Three members of the ST6 microcontroller family: ST62E01, ST62E20, ST62E25
ST6 architecture
The ST6 has 64 bytes of RAM and 4096 bytes of program ROM. Larger amounts are accessed by bank-switching the low 2K section of the ROM.
The RAM address space is actually 256 bytes, divided as follows:
0–63: Not implemented
64–127: Bank-switchable window into program ROM and data EPROM.
128–191: General-purpose RAM
192–255: Peripheral control registers (GPIO ports, timers, etc.) The accumulator is mapped at address 255, but is more commonly addressed implicitly.
Not mapped into the address space is a 12-bit program counter and an associated hardware stack (four or six levels deep, depending on model). There are only two status bits (carry and zero), and they are banked based on processor mode, with separate status bits for normal, interrupt and non-maskable interrupt operation.
The first four general-purpose RAM locations are also known as the X, Y, V and W registers, and some instructions can access them using special short addressing modes. The X and Y registers serve as index registers, and can use indirect addressing modes (X) and (Y).
The instruction set consists of one byte of opcode, followed by up to two one-byte operands. The instruction set can be summarized as follows:
†: ^ ab Confusingly, different models of the ST6 family use different conventions for the value of the carry bit after a subtraction. ST60 processors use the "carry" convention, which clears the bit if the subtract underflows, while the ST62 and ST63 processors use the "borrow" convention, which sets the bit in that case.[3]: 21–22,42
The ST7 has six registers: the accumulator, X and Y index registers, stack pointer, program counter, and condition code register. Also, double-indirect addressing allows the zero page of RAM to serve as additional registers. An unusual but useful feature is that an interrupt pushes four of these registers on the stack (A and X as well as the usual PC and CC), and interrupt return restores them.
ALU instructions fall into two categories, two-operand and one-operand.
Two-operand instructions use the accumulator as the first source. The addressing mode specifies the second source, which may be:
8-bit immediate
8-bit absolute address
16-bit absolute address
Indexed (X)
Indexed plus 8-bit offset (address8,X)
Indexed plus 16-bit offset (address16,X)
The destination is usually the accumulator, but a few instructions modify the second source. (Immediate operands are forbidden in such cases.)
One-operand instructions use the specified operand for both source and destination. The operand may be:
The accumulator A
The X register
8-bit absolute address
Indexed (X)
Indexed plus 8-bit offset (address8,X)
Register plus offset computes a full-width sum, so the 8-bit form may address memory up to 255+255 = 510.
In addition to the above, there are three prefix bytes which may be prepended to any instruction for which they make sense:
PDY (0x90) changes all references to the X register to Y. This allows (Y), (address8,Y) and (address16,Y) addressing modes. This affects implicit operands as well, so the "load X" instruction becomes "load Y". A consequence of this is that load X can only use the X-relative addressing modes, and load Y can only use the Y-relative ones.
PIX (0x92) adds an indirection step to the instruction. The 8- or 16-bit address following the opcode byte is replaced by an 8-bit address of a memory location which holds an 8- or 16-bit address (the latter in big-endian order). This may then be indexed by the X register as usual. This allows (address8), (address16), ([address8],X) and ([address8.w],X) addressing modes.
PIY (0x91) combines the above effects. This allows the ([address8],Y) and ([address8.w],Y) addressing modes. (It may also be used with other modes as part of the "load Y" and "store Y" instructions.)
