The GE-600 series is a family of 36-bitmainframecomputers originating in the 1960s, built by General Electric (GE). When GE left the mainframe business the line was sold to Honeywell, which built similar systems into the 1990s as the division moved to Groupe Bull and then NEC.
The 600-series CPU operates on 36-bit words,[1]: II-17 and addresses are 18 bits. The accumulator Register (AQ) is a 72-bit register that can also be accessed separately as two 36-bit registers (A and Q) or four 18-bit registers (AU,AL,QU,QL).[1]: II-5 An eight-bit Exponent Register contain the exponent for floating-point operations (the mantissa is in AQ).[1]: II-5 There are eight eighteen-bit index registers X0 through X7.[1]: II-5
The 18-bit Base Address Register (BAR) contains the base address and number of 1024-word blocks assigned to the program.[1]: II-7 The system also includes several special-purpose registers: an 18-bit Instruction Counter (IC) and a 24-bit Timer Register (TR) with a resolution of 15.625 μs.[1]: II-5-II-7
Instruction formats
The 600-series machine instructions are one word long. Operand addresses point either to operands or to indirect words, which contain the actual operand address and additional information.
Most instructions have the following format:[1]: II-23
1 1 2 2 2 2 3 3
0 7 8 6 7 8 9 0 5
+------------------+---------+-+-+-+------+
| Y | OP |0|I|0| Tag |
+------------------+---------+-+-+-+------+
Y is the address field (18 bits).
OP is the opcode (9 bits).
I is the interrupt inhibit bit.
Tag indicates the type of address modification to be performed.
The Repeat, Repeat Double, and Repeat Link instructions have a different format.[1]: II-23
Addressing modes
The 600 series has an elaborate set of addressing modes, many of which use indirect words, some of which are auto-incrementing or auto-decrementing. Multiple levels of indirect addressing are supported. Indirect addresses have the same format as instructions, and the address modification indicated by the tag field of the indirect address are performed at each level.[1]: II-23
The tag field of the instruction consist of a 2-bit tag modifier (tm) and a 4-bit tag designator (td).[1]: II-24 The tag modifier indicates the type of modification to be performed on the instruction address:[1]: II-25
Register (R): Add the address field (Y) to the contents of the register indicated by the tag designator.
Register then indirect (RI): Perform the address modification as in Register modification, use the word at the effective address as an indirect address of the operand.
Indirect then register (IR): Obtain the indirect word from the address specified by Y, and perform the modification requested by the tag field of the indirect word. This may result in multiple levels of indirection. Perform the address modification specified by the instruction on the last indirect word encountered.
Indirect then tally (IT): Obtain the indirect word from the address specified by Y, then use the address in the indirect word as the effective address. Bits 30-35 of the indirect word contained a tally field which could be used for addressing characters within a word.
For modification types R, RI, and IR the tag designator contains a register to be used for indexing (X0-X7,AU,AL,QU,QL,IC). Other TD values indicate that Y should be used as an immediate operand. Direct addressing is a special case where Y is used as the operand address with no modification.[1]: II-26
For modification type IT, the indirect word contains an 18-bit address, a 12-bit tally, and a 6-bit tag. The tag designator indicates the operation to be performed, some of which increment the address and decrement the tally of the indirect word or decrement the address and increment the tally of the indirect word. The Character from Indirect and Sequence Character operations can be used to address 6-bit and 9-bit bytes; this supports extracting specific bytes, and incrementing the byte pointer, but not random access to bytes.[1]: II-26-II-33a [2]
Data formats
Data was stored in big-endian format. Bits were numbered starting from 0 (most-significant) to 35 or 71 (least-significant).[3]
Binary fixed-point data was stored in twos-complement. Half-word (18-bits), word (36-bits) and double-word (72-bits) operands were supported. Multiply and divide instructions were provided which would treat the operand as a binary fraction rather than an integer.
Binary floating-point data could be single precision (36 bits) or double precision (72 bits). In either case the exponent was eight bits, twos-complement binary. The mantissa was either 28 or 64 bits, twos-complement binary. Operands and results in the AQ and E registers have up to 72 bis of mantissa.
Character data was either 6-bit BCD or 9-bit ASCII.
I/O
The 600-series also included a number of channel controllers for handling I/O. The CPU could hand off short programs written in the channel controller's own machine language, which would then process the data, move it to or from the memory, and raise an interrupt when they completed. This allowed the main CPU to move on to other tasks while waiting for the slow I/O to complete, a primary feature of time sharing systems.
Operating systems
Originally the operating system for the 600-series computers was GECOS, developed by GE beginning in 1962. GECOS was initially a batch processing system, but later added many features seen on more modern systems, including multitasking and multi-user support.
Between 1963 and 1964, GE worked with Dartmouth College on their Dartmouth BASIC project, which also led to the development of a new timesharing system to support it on the GE-235. This was a great success and led to a late 1967 proposal for an improved version of the system running on the 635. The first version, known to Dartmouth as "Phase I" and GE as "Mark II", the original on the GE-235 becoming "Mark I", was a similar success. "Phase II" at Dartmouth was released as the Dartmouth Time Sharing System (DTSS), while GE further developed Mark II into the improved Mark III.
The precursor of General Electric Information Services began as a business unit within General Electric formed to sell excess computer time on the computers used to give customer demos. In 1965, Warner Sinback recommended that they begin to sell time-sharing services using the time-sharing system (Mark 1) developed at Dartmouth on a General Electric 265 computer. The service was an instant success and by 1968, GEIS had 40% of the $ 70 million time-sharing market. The service continued to grow, and over time migrated to the GE developed Mark II and Mark III operating systems running on large mainframe computers.
The GE Mark II operating system (later Mark III) was used by GE Information Services as the basis for its timesharing and networked computing business. Although Mark II / Mark III was originally based on the Dartmouth system, the systems quickly diverged. Mark II/III incorporated many features normally associated with on-line transaction-processing systems, such as journalization and granular file locking. In the early-to-mid-1970s, Mark III adopted a high-reliability cluster technology, in which up to eight processing systems (each with its own copy of the operating system) had access to multiple file systems.
The Multics operating system was begun in 1964 as an advanced new operating system for the 600 series, though it was not production-ready until 1969. GE supplied the hardware to the project and was one of the development partners (the others were Massachusetts Institute of Technology and Bell Labs). GE saw this project as an opportunity to clearly separate themselves from other vendors by offering this advanced OS which would run best only on their machines. Multics required a number of additional features in the CPU to be truly effective, and John Couleur was joined by Edward Glaser at MIT to make the required modifications. The result was the GE 645, which included support for virtual memory. Addressing was modified to use an 18-bit segment in addition to the 18-bit address, dramatically increasing the theoretical memory size and making virtual memory much easier to support.
History
The GE-600 line of computers was developed by a team led by John Couleur out of work they had done for the military MISTRAM project in 1959. MISTRAM was a radar tracking system that was used on a number of projects, including Project Apollo. The Air Force required a data-collection computer to be installed in a tracking station downrange from Cape Canaveral. The data would eventually be shared with the 36-bit IBM 7094 machine at the Cape, so the computer would likely have to be 36-bits as well. GE built a machine called the M236 for the task, and as a result of the 36-bit needs, it ended up acting much like the 7094.
GE originally had not intended to enter the commercial computer market with their own machine. However, by the early 1960s GE was the largest user of IBM mainframes,[5] and producing their own machines seemed like an excellent way to lower the costs of their computing department. In one estimate, the cost of development would be paid for in a single year free of IBM rental fees. Many remained skeptical, but after a year of internal wrangling, the project to commercialize the M236 eventually got the go-ahead in February 1963.
The machine was originally offered as the main GE-635, and the slower but compatible GE-625 and GE-615. While most were single-processor systems, the 635 could be configured with four CPUs and up to four input/output controllers (IOC's) each with up to 16 Common Peripheral Interface Channels. The 635 was likely the first example of a general purpose SMP system, though the GECOS/GCOS software treated the processors as a master and up to three slaves.
In August 1964, IBM considered the GE 600 series to be "severe competition in the medium and large-scale scientific areas".[6] In May 1965 the first GE-625 computer was delivered to the GE Schenectady plant to replace five other computers of various sizes and makes.[7] A number of GE 635's were shipped during 1965 including two to Martin Marietta in November.[8]
The 600 line consisted of six models: the 605, 615, 625, 635, 645, and 655. GE offered a box to connect to the 635 called a 9SA that allowed the 635 to run 7094 programs.
The 615 was a 635 with Control Unit (CU) and Operations Unit (OU) overlap disabled, and a 36-bit-wide memory path. The 625 was a 635 with Control Unit and Operations Unit overlap disabled and 72-bit-wide memory path. The 635 had a 72-bit-wide memory path and CU/OU overlap enabled. The difference between these models was fewer than 10 wires on the backplane. Field service could convert a 615 to a 635 or 625 or vice versa in a couple of hours if necessary; other than those few wires, the 615, 625 and 635 were identical. The 605 was used in some realtime/military applications and was essentially a 615 without the floating point hardware. Programs coded for a 605 would run without any modification on any other 600 line processor. The 645 was a modified 635 processor that provided hardware support for the Multics operating system developed at MIT.
Continuing problems with the reliability of the magnetic tape systems used with the system cast a pall over the entire project. In 1966 GE withdrew the 600 series from active marketing, there was also widespread redundancies in the Phoenix operation, the issues with the 600 series damaged GE's reputation in the computer industry[10] and resulted in the outright cancellations of a number of orders orders placed for it. By 1967 these problems were cleared up, and the machines were re-launched along with an upgraded version of the GECOSoperating system.
A follow-on project to create a next-generation 635 started in 1967. The new GE-655 replaced the individual transistors from the earlier models with integrated circuits, which doubled the performance of the machine while also greatly reducing assembly costs. However, the machine was still in development in 1969, and was announced but probably never delivered under that name.
By that time the Multics project had finally produced an operating system usable by end-users. Besides MIT, Bell Labs, and GE, GE-645 systems running Multics were installed at the US Air ForceRome Development Center, Honeywell Billerica, and Machines Bull in Paris. These last two systems were used as a "software factory" by a Honeywell/Bull project to design the Honeywell Level 64 computer.
GE sold its computer division to Honeywell in 1970, who renamed the GE-600 series as the Honeywell 6000 series. The 655 was officially released in 1973 as the Honeywell 6070 (with reduced performance versions, the 6030 and 6050). An optional Decimal/Business instruction set was added to improve COBOL performance. This was the Extended Instruction Set, also known as EIS, and the Decimal Unit or DU. The machines with EIS were the 'even' series, the 6040, 6060, 6080 and later the 6025. Several hundred of these processors were sold. Memory was initially 600 ns ferrite core made by Lockheed. Later versions used 750 ns MOS memory. The two could co-exist within a system, but not within a memory controller.
A version of the 6080 with the various Multics-related changes similar to the 645 was released as the 6180. A few dozen 6180-architecture CPUs were shipped. Later members of the 6000 series were released under various names, including Level 66, Level 68, DPS-8, DPS-88, DPS-90, DPS-9000 by Honeywell, Groupe Bull, and NEC.
^Gandy, Anthony; Edwards, Roy (11 Jul 2016). "Enterprise logic vs product logic: the development of GE's computer product line". Business History. 59 (3): 431–452. doi:10.1080/00076791.2016.1205033.
