Fujio Masuoka (舛岡 富士雄, Masuoka Fujio, born May 8, 1943) is a Japanese engineer, who has worked for Toshiba and Tohoku University, and is currently chief technical officer (CTO) of Unisantis Electronics. He is best known as the inventor of flash memory, including the development of both the NOR flash and NAND flash types in the 1980s.[1] He also invented the first gate-all-around (GAA) MOSFET (GAAFET) transistor, an early non-planar 3D transistor, in 1988.
Masuoka was excited mostly by the idea of non-volatile memory, memory that would last even when power was turned off. The EEPROM of the time took very long to erase. He developed the "floating gate" technology that could be erased much faster.
He filed a patent in 1980 along with Hisakazu Iizuka.[5][3]
His colleague Shoji Ariizumi suggested the word "flash" because the erasure process reminded him of the flash of a camera.[6]
The results (with capacity of only 8192 bytes) were published in 1984, and became the basis for flash memory technology of much larger capacities.[7][8] Masuoka and colleagues presented the invention of NOR flash in 1984,[9] and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.[10] Toshiba commercially launched NAND flash memory in 1987.[11][12] Toshiba gave Masuoka a few hundred dollar bonus for the invention, and later tried to demote him.[13] But it was the American company Intel which made billions of dollars in sales on related technology.[13] Toshiba's press department told Forbes that it was Intel that invented flash memory.[13]
He has a total of 270 registered patents and 71 additional pending patents.[3] He has been suggested as a potential candidate for the Nobel Prize in Physics, along with Robert H. Dennard who invented single-transistor DRAM.[21]
^F. Masuoka; M. Asano; H. Iwahashi; T. Komuro; S. Tanaka (December 9, 1984). "A new flash E2PROM cell using triple polysilicon technology". 1984 International Electron Devices Meeting. IEEE. pp. 464–467. doi:10.1109/IEDM.1984.190752. S2CID25967023.
^Masuoka, F.; Momodomi, M.; Iwata, Y.; Shirota, R. (1987). "New ultra high density EPROM and flash EEPROM with NAND structure cell". Electron Devices Meeting, 1987 International. IEDM 1987. IEEE. doi:10.1109/IEDM.1987.191485.
^Yang, B.; Buddharaju, K. D.; Teo, S. H. G.; Fu, J.; Singh, N.; Lo, G. Q.; Kwong, D. L. (2008). "CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs". ESSDERC 2008 - 38th European Solid-State Device Research Conference. pp. 318–321. doi:10.1109/ESSDERC.2008.4681762. ISBN978-1-4244-2363-7. S2CID34063783.