Draft:Rivos

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Draft:Rivos
  • Comment: Github links cannot be used to demonstrate notability. Devonian Wombat (talk) 02:21, 13 May 2026 (UTC)


Rivos Inc was an American fabless semiconductor company based in Santa Clara, CA. It developed SoCs featuring a high-performance server-class RISC-V CPU and a CUDA compatible GPU with unified memory and cache coherence between them.[1].

Rivos
TypePrivate
IndustrySemiconductors
FoundedMay, 2021
Founders
  • Puneet Kumar
  • Mark Hayter
  • Belli Kuttanna
Headquarters
Santa Clara, California
,
US
Websiterivosinc.com

Rivos was founded in 2021 by Puneet Kumar, Mark Hayter, and Belli Kuttanna with Lip-Bu Tan taking credit for bringing them together to start the company [2].

It never launched a product, but Rivos did tapeout an SoC on a TSMC 3 nm process and had IP deals with Meta before being acquired by them in 2025 [2][3][4]. Rivos was also a prominent member of the RISC-V open source community, being a premier member of RISC-V international[5] with Mark Hayter on the board of directors[6], and a founding member of the RISC-V Software Ecosystem Project[7].

History

After founding into stealth mode in 2021, there was very little public information. SemiAnalysis reported on the Linkedin listings of employees showing a wide range of experience from DEC, P.A. Semi, Intel, Apple, Google and more[8].

Less than a year after founding in April of 2022, Apple filed a civil suit against Rivos and 2 employees claiming "Rivos began a coordinated campaign to target Apple employees with access to Apple proprietary and trade secret information about Apple’s SoC designs"[9]. This led to 2 years of legal disputes that resolved after an out-of-court settlement[10].

Over 4 years that the company operated, Rivos raised at least $370 million. This comes from a $120 million Series A funding round in April of 2022[11], $250 million Series A3 in April of 2024 with Matrix Capital leading[12]. They were planning on raising another $500 million[13], but they instead decided to merge with Meta.

Notable Employees

Bob McNamara (credited with the improved xterm ANSI parser), Kristian Høgsberg Kristensen (Creator of Wayland)[14]. Palmer Dabbelt, one of the original members of the UC Berkeley lab that created RISC-V and RISC-V maintainer of Linux, Binutils, GDB, and QEMU. Tse-Yu Yeh famous for introducing two level branch prediction algorithms[15]

Open Source Contributions

Throughout the duration of the company, Rivos contributed extensively to open source tools like Linux, GCC, Binutils, GDB, LLVM, as well as to the RISC-V International standards body and to the RISC-V Software Ecosystem.

RISC-V International ratified extensions proposed during the time of employment at Rivos
Extension Common Name
Zalasr[16] Atomic Load-Acquire and Store-Release Instructions
Svrsw60t59b[17] PTE Reserved for SW bits 60:59
Smctr/Sscctr[18] Control transfer records
Svvptc[19] Obviating Memory-Management Instructions after Marking PTEs Valid
Ssqosid[20] Capacity and Bandwidth Controller QoS Register Interface
Smcntrpmf[21][22] Cycle & Instret Privilege Mode Filtering
Vb[23][24] B Standard Extension
Smcdeleg/Ssccfg[25] Counter Delegation
Smcsrind/Sscsrind[26][27] Indirect CSR Access
Ssqosid[28] Quality-of-Service
Svvptc[19] Eliding Memory-Management Fences on Making PTEs Valid
Svadu[29][30] Hardware Updating of PTE A/D Bits
Zaamo/Zalrsc[31] Atomic Memory Operations/Load-Reserved/Store-conditional
Zabha[32] Byte and Halfword Atomic Memory Operations
Zacas[33][34] Atomic Compare-and-Swap
Zicfiss, Zicfilp[35] Control Flow Integrity
Zimop, Zcmop[36][37] Maybe-ops
IOMMU[38] IOMMU
Zawrs[39][40] Wait-on-Reservation-Set
Vector Crypto[41] Vector Crypto
SBI[42] Supervisor Binary Interface
RAS[43] RAS Error-record Register Interface
ACPI FFH[44] ACPI Fixed Function Hardware

Patent Applications

Patent ID
Flush-on-demand processor instruction trace US20240078115A1
Voltage glitch detector WO2025076373A1
Processor performance profiling using trace actions US20240193070A1
Defectivity redundancy for memory arrays WO2025054241A1
Fast decoding of compressed data US20250085852A1
Hardware data prefetchers for processors WO2025231479A1
Scheduler and table to manage branch divergence WO2025250820A1
Stream processing for encrypted, integrity and replay-protected memory WO2024145348A1
Processor with delayed instruction pipeline flush WO2024137374A1
Error detection or correction using signed parity codes WO2024124115A1

References

  1. ^ "Features". Rivos Inc. Archived from the original on 2025-11-12. Retrieved 2026-03-14.
  2. ^ a b "From Idea to Exit: The Story of Rivos". Walden Catalyst. Retrieved 2026-03-14.
  3. ^ Mark, Hayter. "The Significance of the RVA23 Profile in Advancing the RISC-V Ecosystem" (PDF). www.twiota.org. Archived from the original (PDF) on 2026-03-13. Retrieved 2026-03-15.
  4. ^ "Meta Is Said to Acquire Chips Startup Rivos to Push AI Effort". Bloomberg.com. Archived from the original on 2025-11-28. Retrieved 2026-03-15.
  5. ^ "RISC-V Members". RISC-V International. Archived from the original on 2025-06-29. Retrieved 2026-03-15.
  6. ^ "RISC-V Board of Directors". RISC-V International. Archived from the original on 2025-07-02. Retrieved 2026-03-15.
  7. ^ "Industry Leaders Launch RISE to Accelerate the Development of Open Source Software for RISC-V". Rivos Inc. Archived from the original on 2025-09-16. Retrieved 2026-03-15.
  8. ^ Patel, Dylan (August 30, 2021). "Rivos Inc | A Chip Off The Old Block? New RISC-V Startup Garners Many Senior CPU Architects From Apple, Google, Marvell, Qualcomm, Intel, and AMD". newsletter.semianalysis.com. Retrieved 2026-03-26.
  9. ^ "Complaint – #1 in Apple Inc. v. Rivos, Inc. (N.D. Cal., 5:22-cv-02637) – CourtListener.com". CourtListener. Retrieved 2026-03-26.
  10. ^ "Stipulation – #391 in Apple Inc. v. Rivos, Inc. (N.D. Cal., 5:22-cv-02637) – CourtListener.com". CourtListener. Retrieved 2026-03-26.
  11. ^ StartupHub.ai. "Rivos Seed (2022) - Rivos". www.startuphub.ai. Retrieved 2026-03-26.
  12. ^ Trueman, Charlotte (2024-04-16). "Chip startup Rivos raises $250m to develop AI server chips". www.datacenterdynamics.com. Retrieved 2026-03-26.
  13. ^ Louise, Nickie (2025-08-13). "AI chip startup Rivos seeks up to $500 million in funding to take on Nvidia - Tech Startups". Retrieved 2026-03-27.
  14. ^ Micheal, Larabel. "The State Of The Wayland Display Server". Phoronix Forums. Archived from the original on 2021-10-20. Retrieved 2026-03-15.
  15. ^ Yeh, Tse-Yu; Patt, Yale N. (1991-09-01). "Two-level adaptive training branch prediction". Proceedings of the 24th annual international symposium on Microarchitecture. MICRO 24. New York, NY, USA: Association for Computing Machinery: 51–61. doi:10.1145/123465.123475. ISBN 978-0-89791-460-4.{{cite journal}}: CS1 maint: periodical has ISBN (link)
  16. ^ "Adding Zalasr to the main spec by mehnadnerd · Pull Request #2091 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  17. ^ "Svrsw60t59b - PTE Reserved for SW bits 60:59 Extension by ved-rivos · Pull Request #543 · riscv-non-isa/riscv-iommu". GitHub. Retrieved 2026-03-15.
  18. ^ "Add Smctr/Sscctr by bcstrongx · Pull Request #1615 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  19. ^ a b "Integrate Svvptc standard extension by ved-rivos · Pull Request #1330 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  20. ^ "Integrated Ssqosid extension by ved-rivos · Pull Request #1705 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  21. ^ "move spec to ratified state · riscvarchive/riscv-smcntrpmf@8ecc327". GitHub. Retrieved 2026-03-15.
  22. ^ "Smcntrpmf chapter integration. by wmat · Pull Request #1273 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  23. ^ "Integrate B standard extension text by ved-rivos · Pull Request #1287 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  24. ^ "Update to Ratified state by ved-rivos · Pull Request #8 · riscv/riscv-b". GitHub. Retrieved 2026-03-15.
  25. ^ "Add Smcdeleg/Ssccfg by bcstrongx · Pull Request #1288 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  26. ^ "move to ratified state · riscvarchive/riscv-indirect-csr-access@1ffa5b8". GitHub. Retrieved 2026-03-15.
  27. ^ "Indirect-csr integration into privileged spec. by wmat · Pull Request #1276 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  28. ^ "Integrate ssqosid extension by ved-rivos · Pull Request #1331 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  29. ^ "update state to ratified by ved-rivos · Pull Request #25 · riscvarchive/riscv-svadu". GitHub. Retrieved 2026-03-15.
  30. ^ "Incorporate Svadu and Svade specs by aswaterman · Pull Request #1209 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  31. ^ "Integrate Zaamo and Zalrsc text by ved-rivos · Pull Request #1304 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  32. ^ "Add Zabha standard extension by ved-rivos · Pull Request #1364 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  33. ^ "update to ratified by ved-rivos · Pull Request #28 · riscvarchive/riscv-zacas". GitHub. Retrieved 2026-03-15.
  34. ^ "Integrate zacas chapter. by wmat · Pull Request #1272 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  35. ^ "Integrate Zicfiss and Zicfilp extensions into Priv. and Unpriv. ISA spec. by ved-rivos · Pull Request #1380 · riscv/riscv-isa-manual". GitHub. Retrieved 2026-03-15.
  36. ^ "Zimop/Zcmop - temporary non-official documentation · Issue #131 · riscv/riscv-cfi". GitHub. Retrieved 2026-03-15.
  37. ^ "Add Zimop/Zcmop draft · riscv/riscv-isa-manual@2463e2a". GitHub. Retrieved 2026-03-15.
  38. ^ "Moving specification to ratified state by ved-rivos · Pull Request #237 · riscv-non-isa/riscv-iommu". GitHub. Retrieved 2026-03-15.
  39. ^ "Ratified · riscvarchive/riscv-zawrs@9ff54f7". GitHub. Retrieved 2026-03-15.
  40. ^ "Initial seeding of zawrs chapter. · riscv/riscv-isa-manual@7662956". GitHub. Retrieved 2026-03-15.
  41. ^ "Update riscv-crypto-spec-vector.adoc · riscv/riscv-crypto@56ed795". GitHub. Retrieved 2026-03-15.
  42. ^ "The SBI v3.0 is ratified now. Update the spec to reflect the status. · riscv-non-isa/riscv-sbi-doc@c33ad9f". GitHub. Retrieved 2026-03-15.
  43. ^ "Update status to Ratified by ved-rivos · Pull Request #51 · riscv-non-isa/riscv-ras-eri". GitHub. Retrieved 2026-03-15.
  44. ^ "Update the document state to ratified. · riscv-non-isa/riscv-acpi-ffh@37ac779". GitHub. Retrieved 2026-03-15.

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