Operand Option–operand separation Operand forwarding Operand isolation Instruction set architecture Pentium F00F bug EVEX prefix VEX prefix WD16 Arithmaurel STM8 Common operator notation ST6 and ST7 IJVM FMA instruction set Arithmetic logic unit PDP-11 architecture Increment and decrement operators MOVHPD MOVDDUP Bitwise operations in C Elvis operator TI-990 PIC instruction listings MOVAPD COP8 Index register Reservation station Comparison of instruction set architectures Tomasulo's algorithm MCS-51 Fexpr Text Executive Programming Language Java bytecode Kenbak-1 Ones' complement XPath 2.0 Register–memory architecture Three-address code X86 instruction listings Operator associa…

ativity Stepped reckoner Polish notation IBM System/3 Intel 8087 Model of computation SSSE3 Ln (Unix) Advanced Vector Extensions Zero flag MMIX TMS9900 Arithmetic shift FCMOV Opcode Toshiba TLCS Truth table Compressed instruction set Arity Logical shift IBM 1400 series Accumulator (computing) Addressing mode Comma operator Clipper architecture Fujitsu A64FX Bit manipulation PILOT CLMUL instruction set Honeywell 6000 series ND812 UNIVAC 490 SPARC Divisor (disambiguation) Disjunct GE-600 series Transport triggered architecture Or Bitwise operation GNU Multiple Precision Arithmetic Library Orthogonal instruction set Oper

ator (computer programming) NaN Operator overloading ALGOL X Machine code Operation XOP instruction set Hazard (computer architecture) Logical disjunction Unary X86 assembly language List of discontinued x86 instructions Sizeof Unary operation One-instruction set computer Unary function Super Harvard Architecture Single-Chip Computer Null coalescing operator 0O Infix notation Stack machine Burroughs Medium Systems IBM 305 RAMAC Operators in C and C++ Thrashing (computer science) Register renaming Logical conjunction Quotient of a formal language Projection (relational algebra) Less-than sign SSE5 Language H MLIR (sof