Early XBurst CPU microarchitectures were based upon the MIPS32 revision 1 and newer models are based on the MIPS32 revision 2 instruction set. It implements an 8-stage pipeline XBurst CPU technology consists of 2 parts:
A RISC/SIMD/DSP hybrid instruction set architecture which enables the processor to have the capability of computation, signal processing and video processing. This includes the Media Extension Unit (MXU), a 32-bit SIMD extension. All JZ47xx series CPUs with Xburst uA support MXU, except for the JZ4730.[1][2]
MXU has its own register set, distinct from the general purpose MIPS registers. It consists of sixteen 32-bit data registers and a 32-bit control register.[3] CPUs which support MXU are used in MIPS Creator single-board computers. They are also present in various tablets, handheld game devices, and embedded devices.
XBurst2 microarchitecture
XBurst2 development was, in summer 2013, expected to be completed by the first half of 2014.[4] However, XBurst2 was eventually introduced in 2020 in the X2000,[5] with the microarchitecture offering a dual-issue/dual-threaded CPU design based on MIPS32 Release 5.[6]
The JZ4730 CPU is used in the Skytone Alpha-400 and its variants.[19] The Jz4720 is utilized in the Copyleft Hardware project Ben NanoNote.[20] Another popular device, the Dingoo gaming handheld, uses the JZ4732, a de facto JZ4740. Game Gadget is using the JZ4750. Velocity Micro T103 Cruz and T301 Cruz 7-Inch Android 2.0 Tablets used JZ4760. The JZ4770 SoC is used in several of the Ainol Novo 7 Android tablets[21] and 3Q Tablet PC Qoo! IC0707A/4A40. JZ4770 SoC is also used in the dedicated handheld Neo Geo X[22] and open source handheld GCW Zero[23] running on OpenDingux.[24] The JZ4780 is used in ImgTec's MIPS based single-board computer (SBC); The Creator CI20[25]